20 Fri.
Room A FA-2: Korea Session-1
FA-1: 3D-3
9:00-10:40
FA1-1
[Session
Invited]
Necessity of Chip on Chip Technology for 3D IC
Hiroshi Ozaki (Sony Corporation, Japan)
FA1-2
Encapsulation Technology by Silicon
Based Cavity with TSV Electrode for Pseudo-SoC
Application
Toshihiko Nagano, Kazuhide Abe, Hiroshi Yamada and
Kazuhiko Itaya (Toshiba Corporation, Japan)
FA1-3
Wafer-level Over Molding Process
Development for a stacked WCSP Package with Through Silicon Vias
(TSVs)
Yoshimi Takahashi, Rajiv Dunne, Yohei Koto, Shoichi
Iriguchi, Masazumi Amagai, Tom Bonifield, Philipp Steinmann and David
Stepniak (Texas Instruments Inc., USA)
FA1-4
Development of Si interposer for 2.5D
advanced package
Satoru Kuramochi1 and Yoshitaka
Fukuoka2 (1Dai Nippon Printing Co., Ltd., and
2Weisti, Japan)
| 10:50-12:30 | FA2-1 | Wetting characteristics of
Cu-xZn layers for Sn-3.0Ag-0.5Cu solders Ji Hyun Lee, Young Min Kim and Young-ho Kim (Hanyang University, Korea) |
| FA2-2 | Cost Effective Coreless
Process for Thinner Substrate Hwa Dong Oh, Young Joo Ko and Sang Hee Kim (Daeduck Electronics, Korea) | |
| FA2-3 | A Novel High-Efficient
Aligning Structure for Optical PCB Interconnection Dong Min Kim, Tae Kyung Lee, Tae Ho Lee and Myung Yung Jeong (Pusan National University, Korea) | |
| FA2-3 | The Effects of Levelers on
3D SiP Copper Via Filling Myung-Won Jung, Ki-Tae Kim and Jae-Ho Lee (Hongik University, Korea) |
FA-3: Korea Session-2
| 13:30-15:35 | FA3-1 | Characteristics of Heat
Dissipation and Light Output Power of High-Power LED Packages Processed
with Various Thermal Via Technologies Min-Young Kim1, Byung-Kyu Yu1, Tak Jeong2, Jun-Seok Ha 3 and Tae-Sung Oh1 (1Department of Materials Science and Engineering, Hongik University, 2Korea Photonics Technology Institute and 3Faculty of Applied Chemical Engineering, Chonnam National University, Korea) |
| FA3-2 | Electrical Properties of
Polymer Solar Cells with PCDTBT:PCBM Active Layer Kun Ho Kim1, Seung Ho Kim1, Young Chul Chang2 and Ho Jung Chang1 (1Dankook University and 2Korea University of Technology and Education, Korea) | |
| FA3-3 | Underfill Thermal and
Mechanical Study with Filler Variation Woong-Sun Lee 1, Jin Yu2 and Kwang-Yoo Byun1 (1Hynix Semiconductor Inc. and 2KAIST, Korea) | |
| FA3-4 | Abrasion Resistance of
Nano Crystal Ni Plated on Mold Cavity Yongbin Sun (Kyonggi University, Korea) | |
| FA3-5 | Cancelled |
FA4: Interconnection-3
| 15:40-17:20 | FA4-1 | Adhesion test for
underfill delamination in flip chip package Keishi Okamoto, Akihiro Horibe and Kazushige Toriyama (IBM Japan, Ltd., Japan) |
| FA4-2 | Mode Counting System for
Die Pull Test Yoshiyuki Arai, Yoshinori Miyamoto, Shinpei Aoki and Kenji Shimatan (Toray engineering Co., Ltd., Japan) | |
| FA4-3 | Improvement of Low-k
Delamination with Substrate Pad Structure for Lead-Free Package
Makoto Okada, Michihiko Ichinose and Kouji Kimbara (Renesas Electronics Corporation, Japan) | |
| TA4-4 | An Acceleration Model with
Thermal Cycle Profile for Pb-free Solder Joint Reliability
Akifumi Yoshimua and Keishi Okamoto(IBM Japan, japan) | |
| FA4-5 | A Unique Low-Ag Alloy
Solder Paste for High-Reliability SMT Applications Masato Shimamura (Senju Metal Industry Co., Ltd., Japan) |
Room B
FB1: Advanced-1
| 9:00-10:40 | FB1-1 | [Session
Invited] (50min.) Development of High-end CPU Packaging for Supercomputer Masateru Koide (Fujitsu Advanced Technologies Limited, Japan) |
| FB1-2 | Wafer level packaging to
address future direct chip attach needs Yoshihiro Tomita 1, Yoko Sekihara1, Jiro Kubota1, Kinya Ichikawa1 and Bob Sankman2 (1Intel K.K., Japan and 2Intel Corp., USA) | |
| FB1-3 | Analysis on Design and
Mechanical Stress of 2.5D Package Interposers Takashi Hisada, Toyohiro Aoki, Junko Asai and Yasuharu Yamada (IBM Japan, Ltd., Japan) |
FB2: Advanced-2
| 10:50-12:30 | FB2-1 | Low Cost fcCSP Based on Cu
Pillar Bernd Karl Appelt1, Harrison Chung 2, Chienfan Chen2, Raymond Wang2 and Mike Hung2 (1ASE Group, USA and 2ASE Group, Taiwan) |
| FB2-2 | Thin SiP and 3D eWLB
(embedded Wafer Level BGA) Technology for Advanced
Packaging S.W. Yoon, Yaojian Lin and Pandi C. Marimuthu (STATS ChipPAC Ltd., Singapore) | |
| FB2-3 | Novel EMI Shielding
Methodology on SiP Module Kuo-Hsien Liao1, Alex Chi-Hong Chan1, Bradford J. Factor2 (1ASE Group, Taiwan and 2ASE Europe, Belgium) | |
| FB2-4 | A multi-die DRAM Package
for Solder-down Memory in UltraBook and Tablet PC Applications
Richard D. Crisp1, Wael Zohni1, Bel Haba2, G. Pelissier3 and V. Bui3 (1Invensas Corporation 2Tessera Intellectual Property Corp., USA and 3Dell Inc., Taiwan) |
FB3: Advanced-3
| 13:30-15:10 | FB3-1 | [Session
Invited] Key Packaging Technologies Progressing Fast This Year Hirofumi Nakajima (Renesas Electronics Corporation, Japan) |
| FB3-2 | Formic Gas Used Cu Surface
Treatment and Low Temperature Direct Bonding Wenhua Yang, Masatake Akaike and Tadatomo Suga (The University of Tokyo, Japan) | |
| FB3-3 | ||
| FB3-4 | Copper Wire Bonding Is a
Viable Interconnection Method Bernd Karl Appelt1, Andy Tseng1, Louie Huang2, Scott Chen2 (1ASE Group, USA and 2ASE Group, Taiwan) |
FB4: Substrate
| 15:40-17:20 | FB4-1 | Challenges to Increasing
Wiring Density for Organic Packaging Substrates Masahiro Tsuriya, Haley Fu and Jim Amold (iNEMI (International Electronics Manufacturing Initiative), USA) |
| FB4-2 | Interposer-embedded
packaging technology, a feasible solution for a thinner form-factor
Ren-Shin Cheng, Yu-Wei Huang, Yin-P0 Hung, Fang-Jun Leu, Pei-Cheng Chang, Tao-Chih Chang and Tai-Hong Chen (ITRI, Taiwan) | |
| FB4-3 | Advanced Low CTE Organic
Package Material for Chip Scale Packaging Masahiro Fukui1, Tomoyuki Yamada1, Kenji Terada1, Yoshihiro Hosoi1, Masaaki Harazono1, Teruya Fijisaki1, Francesco Preda2, Jean Audet2, Sushumna Iruvanti2, Shidong Li2, Scott Moore2, Charles Reynolds2 (1KYOCERA SLC Technologies Corporation, Japan and 2 International Business Machines Corporation, USA) | |
| FB4-4 | Warpage Resolution for
Ball Grid Array (BGA) Package in a Fully Integrated
Assembly Alvin Binza Denoyo (Cypress Manufacturing Limited, Philippines) | |
| FB4-5 | Adhesion Characteristics
of Magnetron-Sputter Deposited Copper on Smooth Cycloolefin for Realizing
High-Performance Printed Wiring Board Tetsuya Goto1, T. Matsuo2, M. Iwaki1, K. Soeda1, R. Hiratsuka1, S. Sugawa1 and T. Ohmi1 (1Tohoku University and 2ZEON Corporation, Japan ) |
Room C
FC1: Interconnection-2
| 9:00-10:40 | FC1-1 | [Session
Invited] (50min.) Achieving Fine Geometry Through Embedded Fabrication & Assembly Chuck E. Bauer (TechLead, USA) |
| FC1-2 | Interfacial phenomena in
barrier layer SiCN / Cu film related to adhesion Satoko ABE, Teruhisa BABA, Kenichi UEOKA, Kouji YONEDA and Jiping YE (NISSAN ARC, LTD., Japan) | |
| FC1-3 | Effect of the
crystallinity of electroplated copper thin films on their mechanical and
electrical reliability Naokazu Murata, N. Saito, K. Suzuki and H. Miura (Tohoku University, Japan) |
FC2: MFG-3
| 10:50-12:30 | FC2-1 | Wire Sweep Analysis for
Copper Wire and Pd-coated Copper Wires in Semiconductor Wirebonding
Technology Huang-Kuang Kung1, Hung-Shyong Chen 1, Ming-Cheng Lu1, Che-Chang Li1, Hong-Meng Ho2 (1Cheng Shiu University, Taiwan and 2Semicon Fine Wire Pte Ltd, Singapore) |
| FC2-2 | Flip-chip Interconnection
by Pre-applied Under-fill Material using Copper Pillar Bumps
Koji Motomura, Hiroki Maruo, Hideki Eifuku and Tadahiko Saka (Panasonic Factory Solutions Co., Ltd., Japan) | |
| FC2-3 | B-stageable no-flow
underfill for fine pitch die to substrate packages Kenichi Tosaka (Namics corporation, Japan) | |
| FC2-4 | Flux Residue Cleaning
Process Optimization for Flip Chip Ball Grid Array
(FCBGA) Noor Azrina Talik1, C.S Foong2, B.K Yap1 and C.Y Ta1(1Univeriti Tenaga Nasional and 2Fresscale Semiconductor Malaysia SDN BH, Malaysia ) |
FC3: Thermal-2
| 13:30-15:10 | FC3-1 | Industrial Need for
Accurate and Reproducible Measurements of Thermal Interface Materials
Andras Vass-Varnai1,2, Zoltan Sarkany1,2, Gabor Farkas2 and Marta Rencz1,2 (1Budapest University of Technology and Economics and 2Mentor Graphics, Hungary) |
| FC3-2 | Developing Preferential
Heat Flow Path in Metal Matrix Composite Makoto Kobashi and Naoyuki Kanetake (Nagoya University, Japan) | |
| FC3-3 | Steady and Transient
Thermal Simulation of GaN Devices for High-Speed Switching Applications
Satoshi Ono1, Shigeru Hiura1, Mauro Ciappa2 and Wolfgang Fichtner2 (1Toshiba Corporation, Japan and 2Swiss Federal Institute of Technology, Switzerland) | |
| FC3-4 | Development and analysis
of the thermoelectric material with intermetallic compound
Li-Ling Liao1,2, Ming-Ji Dai1, Chun-Kai Liu1, Jing-Yao Chang1 and Kuo-Ning Chiang2,3 (1ITRI, 2National Tsing Hua University and 3National Center for High-Performance Computing, Taiwan) |
FC4: Thermal-3
| 15:40-17:20 | FC4-1 | Transient Heat Conduction
Simulation of the Microprocessor - Investigation regarding Thermal Control
with Power Limiting Koji Nishi (AMD Japan Ltd., Japan) |
| FC4-2 | TUse Isothermal Surface to
help understanding the Spatial Representation of Structure
Function Yafei Luo (Mentor Graphics Japan, Japan) | |
| FC4-3 | The Development of aHSBGA
Simon Wang1, Scott Chen1, Coltrane Lee 1, Robin Cheng1, TS Chen1 and Andy Tseng2 (1ASECL, Inc., Taiwan and 2ASE US, USA) | |
| FC4-4 | A Method of High Accuracy
Prediction of Θjb and Θjc from Θja through
Thermal Network Analysis Kenichi Inaba and M. Yoshikawa (NEC Corporation, Japan) |
Room D
FD1: DMR-3
| 9:00-10:40 | FD1-1 | Reliability Study of
Thick-film Pressure Sensor on Steel Substrate Zongyang Zhang1,2 and Sheng Liu1,2 (1Huazhong University of Science & Technology and 2Wuhan National Laboratory for Optelectronics, China) |
| FD1-2 | A Thermal Model for
Non-linear Distortion in Printed Circuit Lines for Condition Monitoring of
Electronics Michael Krueger1, Andreas Middendorf 1, Nils F. Nissen2, Herbert Reichl1 and Klaus-Dieter Lang1 (1Technische Universitaet Berlin and 2Fraunhofer IZM, Germany) | |
| FD1-3 | An Analysis of Failure of
Microelectronic Packaging due to Conductive Anodic Filament
Formation Jan-Rong Yang and Mei-Ling Wu (National Sun Yat-Sen University, Taiwan) |
FD2: DMR-4
| 9:00-10:40 | FD2-1 | Innovative 4Layer CPU
Package Design to Enable Low Cost Platform Solution Chan Kim LEE, Chin Lee KUAN and Howe Yin LOO (Intel Microelectronics (M) Sdn. Bhd., Malaysia) |
| FD2-2 | ||
| FD2-3 | An Innovative Motherboard
Concept to Enable Low Cost Package Decoupling Solution Howe Yin LOO and Chan Kim LEE (Intel Microelectronics (M) Sdn. Bhd., Malaysia) | |
| FD2-4 | A New Proposal for
Representing the Process of Electronics Packaging Using DSM
Keiichi Ohizumi and Atsushi Maeda (O2, Japan) |
FD3: DMR-5
| 13:30-15:10 | FD3-1 | On-die PDN Response
Observation of a 6.4Gbps SerDes Device by Direct Excitation from an
External Signal Source and the System-Level PDN Modeling
Masahiro Toyama, Ryuichi Oikawa, Motoo Suwa and Atsushi Nakamura (Renesas Electronics Corporation, Japan) |
| FD3-2 | Characterization of
Electromagnetic Noise Coupling in DC-DC Converter Module
Keisuke Sawada, Masaya Tanaka, Shuji Sagara and Tatsuya Ikeuchi (Dai Nippon Printing Co., Ltd., Japan) | |
| FD3-3 | Icc(t) Modeling
Methodology for High-Speed DDR Power Integrity Design Heng Chuan Shu and Fern Nee Tan (Intel Microelectronics (M) Sdn Bhd, Malysia) | |
| FD3-4 | Does Power Rail Merger
work for High Speed I/O interfaces like PCIe, SATA and
USB? Fern Nee Tan (Intel Microelectronics (M) Sdn Bhd, Japan) |
FD4: DMR-6
| 15:40-17:20 | FD4-1 | Evaluation of 6.4 Gbps
Single-ended Interface through a Standard DIMM
Connector Keisuke Saito and Arun Vaidyanath (Rambus, Inc., USA) |
| FD4-2 | Design and Analysis of
Power Delivery Network in an SoC: A Review Li Wern Che (Intel Microelectonics (M) Sdn. Bhd., Malaysia) | |
| FD4-3 | A Novel High-Frequency
Analysis and Modeling for Printed-Circuit Boards Using the Enhanced
Optimized Segment Extraction Method with Multi-Port
S-Parameter Hirobumi Inoue1 and Kazuhiko Honjo2 (1NEC System Jisso Technologies Research Laboratories and 2The University of Electro-Communications, Japan) | |
| FD4-4 | Extension of EOSE Method
to Weak Nonlinear Systems and Its Application to InGaP/GaAs HBT MMIC
Parallel Tracks Hirobumi Inoue1, Ryo Ihikawa2 and Kazuhiko Honjo2 (1NEC System Jisso Technologies Research Laboratorie and 2The University of Electro-Communications, Japan) | |
| FD4-5 | Measurement and Simulation
of Transmission Characteristic for Interconnect Structure Using 30μm Pitch
Microbump Array on Coplanar Waveguide Yotaro Yasu1,2, Katsuya Kikuchi2, Fumiki Kato2, Shunsuke Nemoto2, Hiroshi Nakagawa2, Kohji Koshiji1 and Masahiro Aoyagi1,2 (1Graduated School Tokyo University of Science and 2AIST) |