Future of Packaging from No Value-add in the Past to High Value-add in the Future Prof. Rao R. Tummala Georgia Institute of Technology

The new era of micro- and nano-electronic systems requires that we define and divide packaging into three distinctly different categories: 1) Semiconductor Packaging of individual devices; 2) package integration of multiple devices by 2D and 3D Packaging that cannot be integrated into monolithic devices; and 3) packaging beyond these devices to form highly-functional and miniaturized systems by Systems Packaging. Semiconductor Packaging was defined [1] in the 1980s as interconnecting, powering, cooling and protecting of active devices. Back then, the focus was primarily on devices, since the device scaling and transistor integration was supposed to have led to System-On-Chip (SOC). But that is not the primary focus today as many of the devices such as RF, Optical, Power and MEMS cannot be integrated into CMOS-based mainstream device technology. Packaging, therefore, must address this integration need. Let's call this 2D and 3D Packaging to interconnect two or more similar or diverse set of devices that cannot be integrated cost effectively into single large SOC chips. This trend started in 1980s when a high performance computing systems required more than 100 similar devices to form a single processor. This led to 2D multi-chip packaging with 100 or more chips interconnected onto a single ceramic or thin film-on-ceramic substrates with lithographic ground rules ranging from 90 microns in thick films to 6 microns in thin films. But systems are more than devices. Only about 20% of systems in volume and cost come from devices. The remaining 80% of the system includes passives, thermal structures, batteries, and interconnection of all these. Let's call this Systems Packaging. Single-chip packaging is the most dominant packaging technology practiced to date starting with lead frame or plastic packaging in the 1970s and moving on to silicon and glass packages in the near future. But its value add at this packaging level to semiconductor companies is minimal, since packaging at a single-chip level adds no benefits either in performance, cost or reliability. It is due to two reasons: to electrically-test the die to guarantee its 100% goodness; and to interconnect the die to other components on the system board by SMT. Packaging at this level can cost more than the device it packages since it involves the package substrate, interconnection, under-fill between the substrate and the die as well as thermal structures. The value-add at this level is very low. For this reason, packaging in the past has been viewed as a necessary evil and single-chip package technology advances have been very cost sensitive and thus are limited. [Read More...]