8:30

TA1: Substrates I

1. Substrates for High Speed Data Transmission (Session Invite)
   S.Denda, Y.Tezuka, Y.Nishioka, Nagano Prefectural Institute of Technology / Japan
    
2. Cancel
    
3. Microvia Technologies in Build-up PWBs
   T.Uusluoto, Tampere University of Technology, P.Jalonen, Satakunta Polytechnic, A.Tuominen, Tampere University of  Technology / Finland
    
4. EcoDesign of Circuit Board Structure
   H. Hayashi, Fujikura / Japan

TB1: Optoelectronics I

1. Unique White LED Packaging Systems
   A.Okuno, Y.Miyawaki, N.Oyama, Sanyu Rec / Japan
    
2. The Narrow Pitch Optical Switch Array which Assembled the Large Mirror onto the Large Stroke Actuator
   K.Miura, T.Numazawa, K.Kawase, Y. Hirata, Sumitomo Electric Industries / Japan
    
3. The Passive Alignment Technique of Fiber-to-waveguide
   B.Choi, M-S. Lee, Information and Communications University, J.Choi, H-I. Lee, C-S. Park, Phoco / Korea
    
4. Analysis of Radiated Emissions from Divided Ground/Power Planes of Opto-electric Boards
   H. Kikuchi, Association of Super-Advanced Electronics Technologies, T. Mori, NTT Advanced Technology, O. Ibaragi, Association of Super-Advanced Electronics Technologies / Japan

10:10

BREAK

10:25

TA2: Interconnection

1. Novel Passive Self-alignment Process Using Liquid Resin Material and Alignment Motion
   J-M. Kim, Osaka University / Japan
    
2. Wire Bonding on Copper/Low K Integrated Circuit - Impact of Cap Metallization
   V.P.Ganesh, M.Sivakumar, V.Kripesh, C.Y. Li, M.K.Iyer, Institute of Microelectronics / Singapore
    
3. Using Anisotropically Conductive Adhesive as Alternative for Soldering in Volume Production
   J.Maattanen, P. Palm, P.Perttula, Elcoteq Network / Finland
    
4. Joining Mechanism and Joint Property by Polymer Adhesive with Low Melting Alloy Filler
   K. Yasuda, Osaka University / Japan

TB2: Materials I

1. Fabrication of Highly Resistive ZnO/Cu Layered Circuit by Chemical Solution Process
   H. Nakamura, NEC Toppan Circuit Solutions, H.Takahashi, S. Yoshihara, Utsunomiya University, Y.Saijyo, C. Uyemura, M.Izaki, Osaka Municipal Technical Research Institute / Japan
    
2. Characterization of TaNx Thin Film Resistor for Optoelectronics Components
   M. Obata, Cimeo Precixion, T.Sakukda, R.Hayashibe, K.Kamimura, Shinshu University / Japan
    
3. Development of Repairable Underfill Resin for Flip Chip Interconnection
   M. Kubo, NEC / Japan
    
4. Reliability of Copper-low K Polyimide Dielectric
   B-S.Chiou, Y-L. Chin, H.Hung, National Chiao Tung University / Taiwan

12:05

Lunch Time

13:05

TA3: Substrates II

1. Solder Reflow Resistance of Thin Thermosetting Adhesives
   K.Kawate, Sumitomo 3M / Japan
    
2. High Density Multilayer Substrate for High Pin Count Flip Chip Packaging Utilizing the Novel Vertical Interconnection Technology
   H.Hara, Sumitomo Bakelite / Japan
    
3. Micro-board Technology Development at the PRC
   F.Liu, V.Sundaram, G.E.White, A.O.Aggarwal, D.Sutter, R.R.Tummala, Georgia Institute of Technology / U.S.A.
    
4. The Modeling and Formulation of Etching Rate Based on Hydrodynamics Theory
   T.Hayashi, IBM Japan / Japan
    
5. Electrical Properties and Reliability of Organic Integral Passives Substrate
   S.Utsumi, Mitsubishi Electric / Japan
    
6. Development of Thin Chip Capacitor to Embed into Organic Package
   Y.Horikawa, Shinko Electric Industries / Japan

TB3: Reliability and Thermal 
Management

1. The Build-up Approach for Thermal Design of Compact Electronic Equipment: The JSME Project Update (Session Invite)
   W.Nakayama, ThermTech International / Japan
    
2. Thermal Fatigue Life Simulation for Sn-Ag-Cu Lead-free Solder Joints
   H.Takahashi, Toshiba / Japan
    
3. Board Level Drop Test and Simulation of QFN Packages for Telecommunication Applications
   T.Y.Tee, H.S.Ng, STMicroelectronics, C.T.Lim, E.Pek, National University of Singapore, Z.Zhong, Nanyang Technological University / Singapore
    
4. Mechanical Bend Fatigue Reliability of Ball Grid Array Assembly with Lead-free Solder
   F.Qi, J.Lin, Motorola (China) Electronics / China, K.Jonnalagadda, Motorola / U.S.A.
    
5. Evaluation of the Reliability of a Large PBGA Assembled on a Build-up Board
   P.Guilbault, University Bordeaux I / Bull SA, E.Woirgard, C.Zardini, University Bordeaux I, D.Lambert, Bull SA / France
    
6. Outline Design Assist Method for Electronics System Thermal Layout by Using Modularized Thermal Simulator
   Y.Iwata, S.Yamamoto, R.Sato, K.Fujimoto, Osaka University / Japan

15:35

Coffee Break

15:50

TA4:Plating and Wafer Treatment

1. Copper Electroplating Applied to Fill High-aspect-ratio Vias for the Application of Three Dimensional Chip Stacking
   S.Oh, T.Yonezawa, K.Kondo, Okayama University, M.Tomisaka, H.Yonemura, M.Hoshino, K.Takahashi, Tsukuba Research Center / Japan
    
2. Dry Desmearing before Ni/Au and Cu Plating by Atmospheric Pressure Plasma
   Y.Sawada, K.Yamazaki, Matsushita Electric Works / Japan
    
3. The Growth Mechanism of P-rich Layer in Interfacial Reaction during Reflow Process of Sn-Ag-Cu Solder on Ni-P/Au Plating
   M.Ito, Toray Research Center / Japan
    
4. Key Challenges in Fine Pitch Bumped Wafer Mechanical Back Grinding and Polishing
   V.P.Ganesh, V.Kripesh, Institute of Microelectronics,/ Singapore, K.Pakiri, G.Itoh, Okamoto Machine Tool Works / Japan
    
5. Stealth Dicing Technology for Ultra Thin Wafer
   F.Fukuyo, Hamamatsu Photonics / Japan
    
6. Au Surface Finish in SMT Field
   W.Wang, J.Liu, Motorola (China) Electronics / China

TB4:Simulation

1. Extracting the Propagation Constants for High-speed Digital Data Transmission on Printed Circuit Boards
   K.Narita, T.Kushta, T.Saeki, H.Tohya, NEC / Japan
    
2. A Study on Signal Transmission Characteristics and Magnetic Near Field Distribution for Differential Two Pair Parallel Signal Lines
   K.Takahashi, T.Kasuga, H.Inoue, Akita University / Japan
    
3. Quasi Differential Signaling for EMI Reduction
   A.Namba, Okayama University / Japan
4. Power Current Modeling of Load Dependency for EMI Simulation
   H.Osaka, Hitachi / Japan
    
5. Thermal-electrical Coupled Analysis on Semiconductor Materials
   C.Azuma, Texas Instruments, Japan / Japan

18:20