ICEP 20th Anniversary Special Lecture

oichikumagai A Stacked Direct Time of Flight Depth Sensor for Automotive LiDAR with SPAD Pixels
Oichi Kumagai

Sony Semiconductor Solutions

In addition to sensing devices such as cameras and millimeter wave radar, LiDAR is becoming ever more important as a method of high-precision detection and recognition of not only road conditions but also the location and shape of objects such as vehicles and pedestrians. This trend is being driven by the popularization of advanced driver assistance systems (ADAS) and the need for this technology in autonomous driving (AD).
SPAD is a pixel structure that uses avalanche multiplication to amplify electrons from a single incident photon, causing a cascade like an avalanche, and it can detect even weak light. It is possible to accomplish long-distance, high-precision distance measuring by employing SPAD as the detector in a dToF sensor, which measures the distance to an object based on the time of flight (time difference) of a light emitted from a light source until it returns to the sensor, after being reflected by the object. Now, by leveraging Sony's technologies such as back-illuminated pixel structure, stacked configurations and Cu-Cu connections cultivated in the development of CMOS image sensors, and achieving the SPAD pixels and distance measuring processing circuitry on a single chip, Sony has succeeded in developing a compact yet high-resolution sensor. This enables high-precision, high-speed measurement at 15-centimeter range resolutions up to a distance of 300 meters. The new development will also help enable detection and recognition under severe conditions such as various temperature and weather as required for automotive equipment, thereby contributing to greater reliability for LiDAR. Achieving a single chip also helps lower the cost of LiDAR.

Belgacem Haba Present and Future of Semiconductor Technology in the Age of Paradigm Shift.
Akihisa Sekiguchi


The year 2020 saw many changes in the way we conduct our lives. As we wrestled with the pandemic that still affects us, transformation took place in the way we work, study, travel and interact with each other in order to cope with the problem. This transformation was enabled in large part by advances in semiconductor technology and ICT (information and communication technology) which took decades to create.
In the talk, the speaker will describe some of the transformation that has taken place (the paradigm shifts), provide an overview on the state of the industry`s process technology used to create essential devices (logic, memory) and talk about the extendibility of technology going forward.
Time permitting, the speaker will also comment on the future direction of computing.

Keynote Lectures

Belgacem Haba Direct Bonding: a new paradigm shift in semiconductor assembly
Belgacem Haba


Moore's law through the years has been the lighting road of the semiconductor industry. For decades it has continued to lead to node shrinking to satisfy the needs, the predictions and the cost of manufacturing. The law has been limited to the 2D wafer design and manufacturing. The increasing desires for more performances of new applications and technologies especially with the upcoming fourth industrial revolution, forged a need of high bandwidth, lower latency, lower thermal and power, and smaller system form factor and all that to be coupled with a lower cost.
Under all these constraints, the continuation of node shrinking has proven to be harder and harder and thus the industry has started to migrate from a 2D to a 3D assembly while keeping the cost in check. The idea of going 3D in assembly is nothing new. Die stacking solutions using wire bonding interconnects using stair die stack NAND or the more recent HBM die stacks using thermo compression bonding of copper pillars with underfill stand as the state of the art in high volume memory applications.
To be true to the technology nomenclature, 3D assembly is no more than a stack to a 2D planar semiconductors where the vertical interconnects are many orders of magnitudes smaller than the 2D interconnects between design blocks within a chip. From this needs a direct bonding interconnect (DBI) emerged as a paradigm shift in the 3D interconnect. This powerful interconnect platform allows design blocks to be allocated in a true 3D fashion. Such a methodology permits reduction of electrical length between blocks, increase the bandwidth by allowing vastly more interconnects per unit area/volume and lower overall power consumption.
In this presentation we will go over the evolution of such a technology and few of its applications whether in wafer to wafer or die to wafer also known as chiplets.

CP Hung Comprehensive SiP Enabling New System Integration
CP Hung

ASE Group

Advanced System in Package (SiP) is offering the system developer comprehensive solutions to differentiate their products to meet various components integration needs. This talk will discuss innovations in SiP technologies - embedded, Flip-Chip, and Fan-Out, describing how the needs are achieved with higher density, smaller form factor and shortened design flow, so very essential for new decade AIoT, 5G, automotive and data center applications.

yasunobunakamura Superconducting Circuits for Quantum Technologies
Yasunobu Nakamura

The University of Tokyo
RIKEN Center for Emergent Matter Science

Superconducting circuits are widely investigated for various applications in quantum information technologies these days. Thanks to the drastic improvement of the coherence properties of superconducting qubits in the last two decades, as well as to their large dipole moment and strong nonlinearity that allow fast control and readout, they are considered to be one of the most promising platforms for implementing quantum information processors flexibly designed on-chip. In addition, based on circuit quantum electrodynamics, qubits are coupled to resonators and waveguides to exploit the properties of those bosonic modes, either localized or propagating. In this talk, I will give an overview of the field and introduce our activities.

Kazuya Okamoto Future View: Technology merger strengthens evolution of semiconductor chips in the hyper-scaling AI/ML era
Kazuya Okamoto

Yamaguchi University
Osaka University

The industry has historically evolved along an S-shaped growth curve and could be explained by Rogers' normal distribution using a diffusion of innovation theory. However, this distribution is changing in the current contestable market created by Big Tech like GAFAM (Google, Amazon, Facebook, Apple and Microsoft). The semiconductor industry, which is a pivotal component of this market, is developing into a new model quite different from the conventional one, especially under the Covid-19 epidemic.
In this keynote lecture, we discuss what a semiconductor should be in the future, based on inductive strategic thinking using IP (Intellectual Property) information and other resources. Specifically, we will review crucial items in the AI/ML (Artificial Intelligence/Machine Learning) era including: 1) Increased costs to shrink transistors and modify their structures, 2) Transition to various 3D strategies to reduce RC delay and power consumption in the interconnects, and to create added value, 3) Importance of integrated metrology using AI/ML, and 4) Need for an optimal solution in the Heterogeneous Integration that combines the design, fabrication process, and high-density packaging with a chiplet and/or panel level concept.
Today, semiconductor technology drivers are changing from conventional Memory and Logic devices to specialized AI chips, and the technology merger of various kinds of design and fabrication fields supports the evolution of these chips.

Kazuya Okamoto Progress of Wafer Level Packaging Technology for RF Devices at 5G Era
Daquan Yu

Xiamen University

As Moore's Law is reaching the limitation, the developing of advanced packaging technology towards to advanced system integration will play key role for semiconductor industry. The development of wafer level packaging technology provides strong support for 5G device integration to meet miniaturization, high performance and low cost. Wafer level Fan-in can be used for SAW/BAW filters and IPD, RF modules. Wafer Level Fan-out can be used for RF modules and mmWave chips. Recently, glass wafer level packaging using through glass via (TGV) technology and embedded glass fan-out (GFO) technology become more and more mature, which can be used for 3D integration for IPD, mmWave, RF module. The advantages of glass wafer packaging include small form factor, low cost, simple process, and excellent electrical performance. This talk will discuss the technologies and challenges of the advanced wafer level manufacturing processes for various 5G applications.